Design of double edge-triggered flip-flop with low power consumption
Department of Electrical Engineering, Hsiuping University of Science and Technology, Taichung 41280, Taiwan.
Review
International Journal of Scholarly Research in Engineering and Technology, 2023, 02(02), 052–059.
Article DOI: 10.56781/ijsret.2023.2.2.0036
Publication history:
Received on 29 April 2023; revised on 06 June 2023; accepted on 09 June 2023
Abstract:
As is well known, the power consumption of integrated circuits (ICs) is considered one of the most important problems for high-performance chips. Accordingly, for any chip design, power consumption has to be taken into account very seriously. In this paper, a low-power double edge-triggered (DET) D-type flip-flop circuit is proposed. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit, and hence requires a small area. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.
Keywords:
D-type flip-flop; Edge-triggered; Integrated circuit; Power consumption
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Copyright © 2023 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0