Single-Port SRAM Cell with lower leakage current in standby mode
Department of Electrical Engineering, Hsiuping University of Science and Technology, Taichung 41280, Taiwan.
Review
International Journal of Scholarly Research in Engineering and Technology, 2023, 02(02), 046–051.
Article DOI: 10.56781/ijsret.2023.2.2.0035
Publication history:
Received on 08 April 2023; revised on 24 May 2023; accepted on 26 May 2023
Abstract:
As is known in the art, it is relatively difficult to write a logic ‘1’ to the five-transistor (5T) static random access memory (SRAM) cell if the SRAM cell currently stores a logic ‘0’. In this paper, we proposed a 5T SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the HVDD supply voltage if the SRAM cell is in a read mode. If the SRAM cell is being written or during a standby mode, the cell voltage control circuit supplies the SRAM cell with the LVDD supply voltage that is less than the HVDD supply voltage. Several HSPICE simulations show that the proposed SRAM cell provides an improvement in SRAM cell topology by providing an efficient solution to the write ‘1’ issue.
Keywords:
Single-Port; SRAM Cell; Reduced Voltage Supply; Writing Operation
Full text article in PDF:
Copyright information:
Copyright © 2023 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0