Design of two-port SRAM cell with improved write operation
Department of Electrical Engineering, Hsiuping University of Science and Technology, Taichung 41280, Taiwan.
Research Article
International Journal of Scholarly Research in Engineering and Technology, 2023, 03(01), 008–015.
Article DOI: 10.56781/ijsret.2023.3.1.0045
Publication history:
Received on 26 June 2023; revised on 05 August 2023; accepted on 07 August 2023
Abstract:
In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near the write bit line. Accordingly, it can provide an efficient solution to the writing ‘1’ issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells and fast writing also can be achieved.
Keywords:
Two-port; Assist circuit; Single-ended; Static random access memory; Read-write control circuit
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Copyright © 2023 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0